/*
 * @Description  : verilog code from HUIYU
 * @authorName   : GuoJi
 * @github       : https://github.com/guoji-kk
 * @gitee        : https://gitee.com/guoji13663585559
 * @email        : 13663585559@163.com
 * @version      : 1.0
 * @Date         : 2023-06-02 13:14:36
 * @LastEditTime : 2023-06-02 13:18:29
 */

`timescale 1ps / 1ps

module present_encryptor_top_tb;

wire [63:0] data_o;
reg  [79:0] data_i;
reg  data_load;
reg  key_load;
reg  clk;

present_encryptor_top UUT (.data_o(data_o),.data_i(data_i),.data_load(data_load),.key_load(key_load),.clk(clk),.encry_ok(encry_ok));

initial
begin
    $monitor($realtime,,"ps %h %h %h %h %h ",data_o,data_i,data_load,key_load,clk);
    #0   data_i = 80'h00000000_00000000_0000 ; key_load = 1; // Key
    #10  data_i = 64'h00000000_00000000      ; key_load = 0; data_load = 1; // Plaintext
    #10  data_load = 0;
    #330 data_i = 80'hFFFFFFFF_FFFFFFFF_FFFF ; key_load = 1; // Key
    #10  data_i = 64'h00000000_00000000      ; key_load = 0; data_load = 1; // Plaintext
    #10  data_load = 0;
    #330 data_i = 80'h00000000_00000000_0000 ; key_load = 1; // Key
    #10  data_i = 64'hFFFFFFFF_FFFFFFFF      ; key_load = 0; data_load = 1; // Plaintext
    #10  data_load = 0;
    #330 data_i = 80'hFFFFFFFF_FFFFFFFF_FFFF ; key_load = 1; // Key
    #10  data_i = 64'hFFFFFFFF_FFFFFFFF      ; key_load = 0; data_load = 1; // Plaintext
    #10  data_load = 0;
    #330 $finish;
end
initial
begin
    clk = 1'b0;
    forever #5 clk = ~clk;
end

endmodule
